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C8051T610/1/2/3/4/5/6/7
17.1.2. EPROM Read Procedure
1. Reset the device using the /RST pin.
2. Wait at least 20 μs before sending the first C2 command.
3. Place the device in core reset: Write 0x04 to the DEVCTL register.
4. Write 0x00 to the EPCTL register.
5. Write the first EPROM address for reading to EPADDRH and EPADDRL.
6. Read a data byte from EPDAT. EPADDRH:L will increment by 1 after this read.
7. (Optional) Check the ERROR bit in register EPSTAT and abort the memory read operation if necessary.
8. If reading is not finished, return to Step 6 to read the next address in sequence, or return to Step 5 to
select a new address.
9. Remove read mode (1st step): Write 0x40 to the EPCTL register.
10.Remove read mode (2nd step): Write 0x00 to the EPCTL register.
11. Reset the device: Write 0x02 and then 0x00 to the DEVCTL register.
17.2. Security Options
The C8051T610/1/2/3/4/5/6/7 devices provide security options to prevent unauthorized viewing of proprie-
tary program code and constants. A security byte in EPROM address space can be used to lock the pro-
gram memory from being read or written across the C2 interface. When read, the RDLOCK and WRLOCK
bits in register EPSTAT will indicate the lock status of the location currently addressed by EPADDR.
Table 17.1 shows the security byte decoding. See Section “14. Memory Organization” on page 77 for the
security byte location and EPROM memory map.
Important Note: Once the security byte has been written, there are no means of unlocking the
device. Locking memory from write access should be performed only after all other code has been
successfully programmed to memory.
Table 17.1. Security Byte Decoding
Bits
7–4
3–0
Description
Write Lock: Clearing any of these bits to logic 0 prevents all code
memory from being written across the C2 interface.
Read Lock: Clearing any of these bits to logic 0 prevents all code
memory from being read across the C2 interface.
Rev 1.1
95
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